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asix electronics corporation frist released date : dec/13/1999 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://ww w.asix.com.tw AX88190al pcmcia fast ethernet mac controller 10/100base pcmcia fast ethernet mac controller document no.: ax190a-13 / v1.3 / june. 27 ? 00 features ieee 802.3u 100base-t, tx, and t4 compatible single chip pc mc i a bus 10/100mbps fast ethernet mac controller embedded 8k * 16 bit sram ne2000 register level compatible instruction compliant with 16 bit pc card standard - february 1995 support both 10mbps and 100mbps data rate support both full-duplex or half-duplex operation provides a mii port for both 10/100mbps operation provides sni i/f for home lan phy or 10m transceiver option support 128 / 256 bytes eeprom (used for saving cis) support automatic loading of ethernet id, cis and adapter configuration from eeprom on power-on initialization external and internal loop-back capability support 8 general purpose i/o ports 128-pin lqfp low profile package 20mhz to 2 5mhz operation, dual 5v and 3.3 v cmos process with 5v i/o tolerance . or pure 3.3v operation *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the AX88190a fast ethernet controller is a high performance and highly integrated pc mc i a bus ethernet controller with embedded 8k*16 bit sram. the AX88190a contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card standard ? february 1995 . the AX88190a implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the AX88190a supports 10mbps/100mbps media-independent interface (mii) and legacy pure 10mbps sni interface to simplify the design. using serial network interface (sni) transceiver, home lan phy or 10base-2 bnc type media can be supported. the AX88190a is built in interface to connect fax/modem chipset with parallel bus interface. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. AX88190a 10/100 phy/txrx modem daa magnetic rj45 rj11 pcmcia i/f eeprom home lan phy or 10m phy/txrx magnetic rj11 or bnc
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 2 contents 1.0 introduction ................................ ................................ ................................ ................................ ............... 5 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ..... 5 1.2 AX88190a b lock d iagram : ................................ ................................ ................................ ............................ 5 1.3 AX88190a p in c onnection d iagram ................................ ................................ ................................ ............. 6 2.0 signal description ................................ ................................ ................................ ................................ .... 7 2.1 pcmcia b us i nterface s ignals g roup ................................ ................................ ................................ ......... 7 2.2 eeprom s ignals g roup ................................ ................................ ................................ ................................ . 8 2.3 mii interface signals group ................................ ................................ ................................ .......................... 8 2.4 sni i nterface pins group ................................ ................................ ................................ ................................ 9 2.5 m odem interface pins group ................................ ................................ ................................ .......................... 9 2.6 g eneral p urpose i/o pins group ................................ ................................ ................................ ..................... 9 2.7 m iscellaneous pins group ................................ ................................ ................................ ............................ 10 2.8 p ower on configuration setup signals cross reference table ................................ ................................ . 11 3.0 memory and i/o mapping ................................ ................................ ................................ ...................... 12 3.1 eeprom m emory m apping ................................ ................................ ................................ .......................... 12 3.2 a ttribute m emory m apping ................................ ................................ ................................ ......................... 12 3.3 i/o m apping ................................ ................................ ................................ ................................ .................... 13 3.4 sram m emory m apping ................................ ................................ ................................ ............................... 13 4.0 registers operation ................................ ................................ ................................ .............................. 14 4.1 pcmcia f unction c onfiguration r egister s et of lan ................................ ................................ ............ 14 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) ................................ ............... 15 4.1.2 configuration and status register of lan (lcsr) offset 3c2h (read/write) ................................ .......... 16 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) ................................ ....... 16 4.2 pcmcia f unction c onfiguration r egister s et of modem ................................ ................................ ..... 17 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) ................................ ....... 17 4.2.2 configuration and status register of modem (mcsr) offset 3e2h (read/write) ................................ .. 18 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) ............................... 18 4.3 mac c ore r egisters ................................ ................................ ................................ ................................ .... 19 4.3.1 command register (cr) offset 00h (read/write) ................................ ................................ .................... 21 4.3.2 interrupt status register (isr) offset 07h (read/write) ................................ ................................ ........... 21 4.3.3 interrupt mask register (imr) offset 0fh (write) ................................ ................................ .................... 22 4.3.4 data configuration register (dcr) offset 0eh (write) ................................ ................................ ........... 22 4.3.5 transmit configuration register (tcr) offset 0dh (write) ................................ ................................ ..... 22 4.3.6 transmit status register (tsr) offset 04h (read) ................................ ................................ ................... 23 4.3.7 receive configuration (rcr) offset 0ch (write) ................................ ................................ .................... 23 4.3.8 receive status register (rsr) offset 0ch (read) ................................ ................................ .................... 23 4.3.9 inter-frame gap (ifg) offset 16h (read/write) ................................ ................................ ........................ 23 4.3.10 inter-frame gap segment 1(ifgs1) offset 12h (read/write) ................................ ................................ .. 24 4.3.11 inter-frame gap segment 2(ifgs2) offset 13h (read/write) ................................ ................................ .. 24 4.3.12 mii/eeprom management register (memr) offset 14h (read/write) ................................ ................. 24 4.3.13 test register (tr) offset 15h (write) ................................ ................................ ................................ ..... 24 4.3.14 general purpose input register (gpi) offset 18h (read) ................................ ................................ ...... 24 4.3.15 general purpose i/o register (gpio) offset 1ah (read/write) ................................ ............................. 25 5.0 pcmcia device access functions ................................ ................................ ................................ .... 26 5.1 a ttribute m emory access function functions . ................................ ................................ ......................... 26 5.2 i/o access function functions . ................................ ................................ ................................ .................... 26
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 3 6.0 electrical specification and timings ................................ ................................ ....................... 27 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ......................... 27 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 27 6.3 dc c haracteristics ................................ ................................ ................................ ................................ ...... 27 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ........................ 28 6.4.1 xtal / clock ................................ ................................ ................................ ................................ ......... 28 6.4.2 reset timing ................................ ................................ ................................ ................................ ............. 28 6.4.3 attribute memory read timing ................................ ................................ ................................ ................. 29 6.4.4 attribute memory write timing ................................ ................................ ................................ ................ 30 6.4.5 i/o read timing ................................ ................................ ................................ ................................ ....... 31 6.4.6 i/o write timing ................................ ................................ ................................ ................................ ....... 32 6.4.7 mii timing ................................ ................................ ................................ ................................ ................ 33 6.4.8 sni timing ................................ ................................ ................................ ................................ ................ 34 7.0 package information ................................ ................................ ................................ ........................... 35 appendix a: application note ................................ ................................ ................................ ................. 36 a.1 u sing c rystal 25mh z or 20mh z ................................ ................................ ................................ ................. 36 a.2 u sing o scillator 25mh z or 20mh z ................................ ................................ ................................ ............ 36 a.3 u sing 60mh z o scillator /c rystal ................................ ................................ ................................ .............. 36 a.4 d ual power (5v and 3.3v) application ................................ ................................ ................................ ....... 37 a.5 s ingle power (3.3v) application ................................ ................................ ................................ ................. 37 a.6 d ual power (5v and 3.3v) application with 3.3v phy ................................ ................................ ............. 38 appendix b: AX88190 design changes to AX88190a ................................ ................................ ........... 39 errata of AX88190a version ed2 ................................ ................................ ................................ .............. 40 demonstration circuit : AX88190a + ethernet phy + homepna 1m8 phy ........................... 41 reference bill of materials ................................ ................................ ................................ .................. 47 sponsors of components ................................ ................................ ................................ ........................... 48 sponsors of components (chinese) ................................ ................................ ................................ ...... 49
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 4 figures f ig - 1 AX88190a b lock d iagram ................................ ................................ ................................ ........................... 5 f ig - 2 AX88190a p in c onnection d iagram ................................ ................................ ................................ ............ 6 tables t ab - 1 pcmcia bus interface signals group ................................ ................................ ................................ ........ 7 t ab - 2 eeprom bus interface signals group ................................ ................................ ................................ ........ 8 t ab - 3 mii interface signals group ................................ ................................ ................................ ........................ 8 t ab - 4 s erial n etwork i nterface pins group ................................ ................................ ................................ ........ 9 t ab - 5 m odem interface signals group ................................ ................................ ................................ .................. 9 t ab - 6 g eneral p ursose i/o pins group ................................ ................................ ................................ ................ 10 t ab - 7 m iscellaneous pins group ................................ ................................ ................................ .......................... 10 t ab - 8 p ower on c onfiguration s etup t able ................................ ................................ ................................ ...... 11 t ab - 9 eeprom m emory m apping ................................ ................................ ................................ ........................ 12 t ab - 10 a ttribute m emory m apping ................................ ................................ ................................ .................... 12 t ab - 11 i/o a ddress m apping ................................ ................................ ................................ ................................ 13 t ab - 12 l ocal m emory m apping ................................ ................................ ................................ ........................... 13 t ab - 13 pcmcia f unction c onfiguration r egister m apping of lan ................................ ............................... 14 t ab - 14 pcmcia f unction c onfiguration r egister m apping of modem ................................ ........................ 17 t ab - 15 p age 0 of mac c ore r egisters m apping ................................ ................................ ................................ . 19 t ab - 16 p age 1 of mac c ore r egisters m apping ................................ ................................ ................................ . 20
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 5 1.0 introduction 1.1 general description: the AX88190a provides industrial standard ne2000 registers level compatable instruction set. various drivers are easy acquired, maintenance and usage with no pain and tears the AX88190a fast ethernet controller is a high performance and highly integrated pc mc i a bus ethernet controller with embedded 8k*16 bit sram. the AX88190a contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card standard ? february 1995 . the AX88190a implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the AX88190a support 10mbps/100mbps media-independent interface (mii) and legacy pure 10mbps sni interface to simplify the design. using serial network interface (sni) transceiver, home lan phy or 10base-2 bnc type media can be supported. the AX88190a is built in interface to connect fax/modem chipset with parallel bus interface. the main difference between AX88190a and AX88190 are : 1) replace memory i/f with sni i/f. 2) fix oe# signal synchronous problem 3) fix interrupt status can ? t always clean up problem of AX88190. 4) add 8 general purpose i/o ports. 5) change mpd_set (pin 74 -> pin 68) and ppd_set (pin 76 -> pin 70) power on setup pins location. AX88190a use 128-pin lqfp low profile package, typical 2 5mhz o peration, dual 5v and 3.3 v cmos process with 5v i/o tolerance or pure 3.3v operation. 1.2 AX88190a block diagram: fig - 1 AX88190a block diagram mac core 8k* 16 sram and memory arbiter remote dma fifos ne2000/gpio registers pcmcia interface sta seeprom loader i/f sd[15:0] sa[9:0] ctl bus mii i/f smdc smdio eecs eeck eedi eedo modem i/f sni i/f gpi/o
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 6 1.3 AX88190a pin connection diagram the AX88190a is housed in the 128-pin plastic light quad flat pack. see fig - 2 AX88190a pin connection diagram . fig - 2 AX88190a pin connection diagram mpwdn 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] mreset# vss mint 107 105 66 65 63 60 25 16 13 3 7 vss mrdy lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd ppwdn maudio mdcs# 28 22 9 hvdd lvdd vss 126 119 110 121 79 74 80 72 46 29 52 10 mrin# 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss iois16# vss 40 37 50 18 14 AX88190a pcmcia 10/100base mac controller 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv rx_er sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] ireq# we# iord# iowr# oe# sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] wait# reset inpack# ce2# ce1# txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs stschg# spkr# reg# vss vss 64 clko scrs srxd srxc slink# stxe stxd stxc scol vss hvdd test hvdd lvdd lvdd vss vss gpio3 gpio2 gpio1# gpio0# nc nc nc nc nc nc nc nc nc nc nc nc nc nc clk_div3# eeprom_size gpi3 gpi2 gpi1 gpi0
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 7 2.0 signal description the following terms describe the AX88190a pin-out: all pin names with the ? # ? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 pcmcia bus i nterface s ignals g roup signal type pin no. description sa [9:0] i 10 ? 1 system address : signals sa[9:0] are address bus input lines which enable direct address of up to 64k memory and i/o spaces on card. sd[15:0] i/o 20 ? 23, 25 ? 38, 30 ? 33, 35 ? 38 system data bus : signals sd[15:0] constitute the bi-directional data bus. ireq# o 12 interrupt request : ireq# is asserted to indicate the host system that the pc card device requires host software service. wait# o 125 wait : this signal is set low to insert wait states during remote dma transfer. reg# i 123 attribute memory and i/o space select : when the reg# signal is asserted, access is limited to attribute memory and to the i/o space. iord# i 15 i/o read : the host asserts iord# to read data from AX88190a i/o space. iowr# i 14 i/o write : the host asserts iowr# to write data into AX88190a i/o space. oe# i 16 output enable : the oe# line is used to gate memory read data from memory on pc card we# i 13 write enable : the we# signal is used for strobing memory write data into the memory on pc card. iois16# o 120 i/o is 16 bit port : the iois16# is asserted when the address at the socket corresponds to an i/o address to which the card responds, and the i/o port addressed is capable of 16-bit access. inpack# o 124 input port acknowledge : the signal is asserted when the AX88190a is selected and can respond to and i/o read cycle at the address on the address bus. ce1 # -ce2 # i 18, 17 card enable : the ce1# enables even numbered address bytes and ce2# enables odd numbered address bytes bvd1_stschg# o 121 battery voltage detect 1 / status change bvd2_spkr# o 122 battery voltage detect 2 / audio speaker out tab - 1 pcmcia b us interface signals group
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 8 2.2 eeprom s ignals g roup signal type pin no. description eecs o 106 eeprom chip select : eeprom chip select signal. eeck o 107 eeprom clock : signal connected to eeprom clock pin. eedi o 108 eeprom data in : signal connected to eeprom data input pin. eedo i /pu 109 eeprom data out : signal connected to eeprom data output pin. tab - 2 eeprom bus interface signals group 2.3 mii interface signals group signal type pin no. description rxd[3:0] i 90 ? 87 receive data : rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i 85 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_dv i 83 receive data valid : rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er i 82 receive error : rx_er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i 86 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the repeater. col i 84 collision : this signal is driven by phy when collision is detected. tx_en o 95 transmit enable : tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 99 ? 96 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_clk i 94 transmit clock : tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o 92 station management data clock : the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 91 station management data input / output : serial data input/output transfers from/to the phys . the transfer protocol conforms to the ieee 802.3u mii specification. tab - 3 mii interface signals group
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 9 2.4 s ni interface pins group signal type pin no. description stxc i 66 transmit clock : this signal is driven by phy with 20mhz clock. stxd o 68 transmit data : stxd is transition synchronously with respect to the rising edge of stxc. for each stxc period in which stxe is asserted, stxd is accepted for transmission by the phy. stxe o 70 transmit enable : stxe is transition synchronously with respect to the rising edge of stxc. stxe indicates that the port is presenting data on stxd for transmission. scol i 76 collision : this signal is driven by phy when collision is detected. srxc i 78 receive clock : srxc is driven by phy for received data synchronization. srxd i 79 receive data : srxd is driven by the phy synchronously with respect to srxc. scrs i 80 carrier sense : asynchronous signal scrs is asserted by the phy when either the transmit or receive medium is non-idle. slink# i/pu 74 link indicator : active low indicate the sni interface is link to network. when sni is not used must keep the pin no connection or pull high the signal. tab - 4 serial network interface pins group 2.5 modem interface pins group signal name type pin no. description mrdy i/pu 118 modem ready : mrdy low indicates that modem is initializing the modem after reset signal asserted or the modem is at sleep/stop mode. mreset # o 117 modem reset : this signal asserts low to reset the modem chipset. mdcs # o 111 modem chip select : this signal connected to modem chip select pin. mpwdn o 116 modem power down : rockwell modem chipset, this signal asserts low to let modem chipset into power down mode. at&t modem chipset, this signal asserts high to let modem chipset into power down mode. mint i/pd 112 modem interrup t : this signal driven by modem chipset to active interrup t . mrin# i/pu 115 ring input : this signal is driven by daa ? s ring detect circuit. when a tel e phone ringing signal is being received. maudio i/pd 113 modem audio : this signal is passed to pcmcia interface via spkr. tab - 5 modem interface signals group 2.6 general purpose i/o pins group signal name type pin no. description gpi[3] i 57 read register offset 18h bit 3 value reflects this input value. gpi[2] i 58 read register offset 18h bit 2 value reflects this input value. gpi[1] i 60 read register offset 18h bit 1 value reflects this input value. gpi[0] i 61 read register offset 18h bit 0 value reflects this input value.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 10 gpio3# i/o 41 default ? 1 ? . the pin reflects register offset 1ah bit 3 inverted value. gpio2 i/o 42 default ? 0 ? . the pin reflects register offset 1ah bit 2 value. gpio1# i/o 43 default ? 1 ? . the pin reflects register offset 1ah bit 1 inverted value. gpio0# i/o 45 default ? 1 ? . the pin reflects register offset 1ah bit 0 inverted value. tab - 6 general pursose i/o pins group 2.7 miscellaneous pins group signal type pin no. description lclk/xtalin i 103 cmos local clock : typical a 25mhz clock, +/- 100 ppm, 40%-60% duty cycle. ( see application note also ) crystal oscillator input : typical a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. xtalout o 104 crystal oscillator output : typical a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko o 101 clock output : this clock is source from lclk/xtalin. clk_div3# i/pu 67 clock devide 3 enable : active low to enable the devided 3 circuit. that internally devides lclk/xtalin input frequeny by 3 and then feed into internal circuit for system clock used. default value set to logic high, this function is disabled. ppwdn o 114 phy power down : this pin connects to phy chip power down mode control input. reset i /pd 127 reset reset is active high then place AX88190a into reset mode immediately. during falling edge the AX88190a loads the eeprom data. test# i/pu 77 test pin : active low the pin is just for test mode setting purpose only. must be pull high when normal operation. eeprom size i/pu 73 eeprom size = 0 : 93c46 128 byte type eeprom is used. eeprom size = 1 : 93c56 256 byte type eeprom is used. nc n/a 46 ? 48, 50 ? 53, 55-56, no connection : for manufacturing test only. lvdd p 44, 54, 100, 110, 126, 128 power supply : +3.3v dc. hvdd p 19, 29, 64, 75 power supply : +5v dc. note : for pure 3.3v single power solution, all the hvdd pin can connect to +3.3v. care should be taken that hvdd input power must be greater or equal ( > = ) than lvdd. vss p 11, 24, 34, 39, 40, 49, 59, 69, 81, 93, 102, 105, 119 power supply : +0v dc or ground power. tab - 7 miscel laneous pins group
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 11 2.8 power on configuration setup signals cross reference table signal name share with description mpd_set stxd mpd_set = 0 : mpwdn pin active high. mpd_set = 1 : mpwdn pin active low. ppd_set stxe ppd_set = 0 : ppwdn pin active high. ppd_set = 1 : ppwdn pin active low. all of the above signals are pull-up for default values. tab - 8 power on configuration setup table
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 12 3.0 memory and i/o mapping there are four memory or i/o mapping used in AX88190a. 1. eeprom memory mapping 2. attribute memory mapping 3. i/o mapping 4. local memory mapping 3.1 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count 01h cfh cfl 02h node-id1 node id 0 03h node id 3 node id 2 04h node id 5 node id 4 05h checksum reserved 06h ? 10h reserved reserved 10h ? ffh cis cis tab - 9 eeprom memory mapping note : bit 3 register of lcor in AX88190 is replaced by bit 0 of cfl in AX88190a bit 0 of cfl : enable power down mode this bit is set to 1, the lan will go into power down mode. at power down mode AX88190a will disable mac transmitting and receiving operation. but the host interface will not be affected. 3.2 attribute memory mapping attribute memory offset contents 00 00 h 03bfh cis 03c0h lcor 03c2h lccsr 03c4h - 03c6h - 03cah liobase0 03cch liobase1 03ceh 03dfh reserved 03e0h mcor 03e2h mccsr 03e4h - 03e6h - 03eah miobase0 03ech miobase1 03eeh 03ffh reserved tab - 10 attribute memory mapping
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 13 3.3 i/o mapping system i/o offset function 00 00 h 001fh mac core register tab - 11 i/o address mapping 3.4 sram memory mapping offset function 00 00 h 03bfh cis *1 03c0h l cor *1 03c2h l ccsr *1 03c4h - 03c6h - 03cah l iobase0 *1 03cch l iobase1 *1 03ceh 03dfh reserved 03e0h mcor *1 03e2h mccsr *1 03e4h - 03e6h - 03eah miobase0 *1 03ech miobase1 *1 03eeh 03ffh reserved 0400h node id 0 0401h node id 1 0402h node id 2 0403h node id 3 0404h node id 4 0405h node id 5 0406h 07ffh reserved 40 00h 7 fffh 8k x 16 sram buffer tab - 12 local memory mapping
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 14 4.0 registers operation the re are three register sets in AX88190a : the pcmcia function configuration registers of lan . the pcmcia function configuration registers of modem . t he mac core register . 4.1 pcmcia function configuration register set of lan register name offset lcor configuration option register 3c 0h l csr configuration and status register 3c2h l iobase0 i/o based register 0 3cah l iobase1 i/o based register 1 3cch tab - 13 pcmcia function configuration register mapping of lan
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 15 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) field r/w/c description 7 r/w software reset assert this bit will reset the lan function of AX88190a . return a 0 to this bit will leave the lan function of AX88190a in a post-reset state as same as that following a hardware reset. the value of this bit is 0 at power-on. 6 r/w level irq this bit should be set to 1, the AX88190a always generates level mode interrupt. 5:0 r/w function configuration index these six bits are used to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc card, bit 5, bit 4, bit 3 : modem i/o base registers bit 5 bit 4 bit 3 lan i/o base modem i/o base 0 0 0 300h decided by miobase registers 0 0 1 320h 2f8h 0 1 0 340h 3e8h 0 1 1 360h 2e8h 1 0 0 380h decided by miobase registers 1 0 1 200h 2f8h 1 1 0 220h 3e8h 1 1 1 240h 2e8h bit 2 : enable ireq# routing if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1, the lan will generate interrupt request via ireq# signal. if this bit is set to 0, the lan will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1,only i/o addresses that are qualified by the base and limit registers are passed to lan function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the lan function is disabled. if this bit is set to 1, the lan function is enabled.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 16 4.1.2 configuration and status register of lan (l cs r) offset 3c2h (read/write) field r/w/c description 7:3 - reserved 2 r/w ppwrdwn : phy power down setting while this bit set to 1, ppwdn pin (pin 114) will be active to force phy chip into power down mode. as for ppwdn is active high or active low. please refer section 2.7 power on configuration setup signal cross reference table. 1 r intr : interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack : interrupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) the i/o base registers (liobase0 and liobase1) determine the base address of the i/o range used to access the lan specific registers (mac core registers). i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 17 4.2 pcmcia function configuration register set of modem register name offset mcor configuration option register 3e 0h m csr configuration and status register 3e2h m iobase0 i/o based register 0 3eah m iobase1 i/o based register 1 3ech tab - 14 pcmcia function configuration register mapping of modem 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) field r/w/c description 7 r/w software reset assert this bit will reset the modem function of AX88190a . return a 0 to this bit will leave the modem function of AX88190a in a post-reset state as same as that following a hardware reset. the value of this bit is 0 at power-on. 6 r/w level irq this bit should be set to 1, the AX88190a always generates level mode interrupt. 5:0 r/w function configuration index these six bits are used to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc card, bit 5, bit4 : reserved bit 3 : mint route to stschg# if bit 0 of mcor is set to 0, this bit is ignored. if both bit 0 and bit 2 of mcor are set to 1 and this bit is set to 1, the modem will route interrupt request to stschg# signal. if this bit is set to 0, the modem will generate interrupt request via ireq# line. bit 2 : mint route to ireq# (enable ireq# routing) if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1, the modem will generate interrupt request via ireq# signal. if this bit is set to 0, the modem will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1,only i/o addresses that are qualified by the base and limit registers are passed to modem function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the modem function is disabled. if this bit is set to 1, the modem function is enabled.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 18 4.2.2 configuration and status register of modem (m cs r) offset 3e2h (read/write) field r/w/c description 7:3 - reserved 2 r/w mpwrdwn : modem power down setting while this bit set to 1, mpwdn pin (pin 116) will be active to force modem chip into power down mode. as for mpwdn is active high or active low. please refer section 2.7 power on configuration setup signal cross reference table. 1 r intr : interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack : interrupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) the i/o base registers (miobase0 and miobase1) determine the base address of the i/o range used to access the modem specific registers. i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 19 4.3 mac core registers all registers of mac core are 8-bit wide and mapped into pages which are selected by ps in the command register. page 0 (ps 1 =0 ,ps0=0 ) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( pstart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisions register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) remote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 0 0ch receive status register ( rsr ) receive configuration register ( rcr ) 0dh frame alignment errors ( cntr0 ) transmit configuration register ( tcr ) 0eh crc errors ( cntr1 ) data configuration register ( dcr ) 0fh missed packet errors ( cntr2 ) interrupt mask register ( imr ) 10h 11h data port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h ? 18h reserved reserved 19h gpi reserved 1ah gpio gpio 1bh - 1eh reserved reserved 1fh reset reserved tab - 15 page 0 of mac core registers mapping
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 20 page 1 ( ps1=0, ps 0 =1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast address register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h 11h data port data port 12h inter-frame gap segment 1 ifgs1 inter-frame gap segment 1 ifgs1 13h inter-frame gap segment 2 ifgs2 inter-frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h ? 18h reserved reserved 19h gpi reserved 1ah gpio gpio 1bh - 1eh reserved reserved 1fh reset reserved tab - 16 page 1 of mac core registers mapping
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 21 4.3.1 command register (cr) offset 00h (read/write) field name description 7 :6 ps 1,ps0 ps 1,ps0 : page select the two bit selects which register page is to be accessed. ps1 ps0 0 0 page 0 0 1 page 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by AX88190a when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address are not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set to initiate transmission of a packet 1 start start : this bit is used to active AX88190a operation. 0 stop stop : stop AX88190a this bit is used to stop the AX88190a operation. 4.3.2 interrupt status register (isr) offset 07h (read/write) field name description 7 rst reset status : set when AX88190a enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overflow set when msb of one or more of the tally counters has been set. 4 ovw over write : set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors excessive collisions fifo under - run 2 rxe receive error indicates that a packet was received with one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted indicates packet transmitted with no error 0 prx packet received indicates packet received with no error.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 22 4.3.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ? low ? disabled. 5 cnte counter overflow interrupt enable. default ? low ? disabled. 4 ovwe overwrite interrupt enable. default ? low ? disabled. 3 txee transmit error interrupt enable. default ? low ? disabled. 2 rxee receive error interrupt enable. default ? low ? disabled. 1 ptxe packet transmitted interrupt enable. default ? low ? disabled. 0 prxe packet received interrupt enable. default ? low ? disabled. 4.3.4 data configuration register ( dcr ) offset 0eh (write) field name description 7 rdcr remote dma always completed 6:2 - reserved 1 bos byte order select 0: ms byte placed on ad15:ad8 and ls byte on ad7-ad0 (80x86). 1: ms byte placed on ad7::ad0 and ls byte on ad15:ad0(68k) 0 wts word transfer select 0 : selects byte-wide dma transfers. 1 : selects word-wide dma transfers. 4.3.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad disable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less tha n 60. 5 rlo retry of late collision 0 : don ? t retransmit packet when late collision happens. 1 : retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 internal nic loop-back mode 2 1 0 phycevisor loop-back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 23 4.3.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the AX88190a aborted transmission because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 4.3.7 receive configuration (rcr) offset 0ch (write) field name description 7 int_rg interrupt regeneration 0 : enable interrupt regeneration function in multifunction application. (default) but must set cis relative enable function first, than the function will be open. 1: disable 6 - reserved 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet will be checked on node address and crc but not buffered into memory. 4 pro pro : promiscuous mode enable the receiver to accept all packets with a physical address. 3 am am : accept multicast enable the receiver to accept packets with a multicast address. that multicast address must pass the hashing array. 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept and save packets with error. 4.3.8 receive status register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact 4.3.9 inter-frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap . default value 15h.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 24 4.3.10 inter-frame gap segment 1 ( ifgs1 ) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 1 . default value 1ch. 4.3.11 inter-frame gap segment 2 ( ifgs2 ) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 2 . default value 11h. 4.3.12 mii/eeprom management register ( memr ) offset 14h (read/write) field name description 7 eeclk eeclk eeprom clock 6 eeo eeo eeprom data out 5 eei eei eeprom data in 4 eecs eecs eeprom chip select 3 mdo mdo mii data out 2 mdi mdi mii data in 1 m dir mii sta mdio signal direction mii read control bit, assert this bit let mdio signal as the input signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock 4.3.13 test register (tr) offset 15h (write) field name description 7 - reserved 6 mpsel media priority select : default value is logic 0 mpsel /slink media selected 0 0 sni 0 1 mii 1 x depand on mpset bit 5 mpset media set by program : the signal is valid only when mpsel is set to high. when mpset is logic 0 , sni is selected. when mpset is logic 1 , mii is selected. 4 tf16t test for collision, default value is logic 0 3 tpe test pin enable , default value is logic 0 2:0 ifg select test pins output , default value is logic 0 4.3.14 general purpose input register ( gpi ) offset 18h (read) field name description 7 :4 - reserved 3 gpi3 this register reflects gpi[3] input value 2 gpi2 this register reflects gpi[2] input value 1 gpi1 this register reflects gpi[1] input value 0 gpi0 this register reflects gpi[0] input value
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 25 4.3.15 general purpose i/o register ( gpio ) offset 1ah (read/write) field name description 7:6 - reserved 5 ctl default ? 1 ? . and must keep it to logic 1 always. 4 - reserved 3 gpio3 default ? 0 ? . the register reflects to gpio3# pin with inverted value. 2 gpio2 default ? 0 ? . the register reflects to gpio2 pin directly. 1 gpio1 default ? 0 ? . the register reflects to gpio1# pin with inverted value. 0 gpio0 default ? 0 ? . the register reflects to gpio0# pin with inverted value.
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 26 5.0 pcmcia device access functions 5.1 attribute memory access function functions. attribute memory read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte not valid word access (16 bits) l l l x l h not valid even-byte odd byte only access l l h x l h not valid high-z attribute memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte x word access (16 bits) l l l x h l x even-byte odd byte only access l l h x h l x x 5.2 i/o access function functions. i/o read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte odd-byte word access (16 bits) l l l l l h odd-byte even-byte i/o inhibit h x x x l h high-z high-z odd byte only access l l h x l h odd-byte high-z i/o write function function mode reg# ce2# ce1# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte odd-byte word access (16 bits) l l l l h l odd-byte even-byte i/o inhibit h x x x h l x x odd byte only access l l h x h l odd-byte x
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 27 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -55 +150 c supply voltage hvdd -0.3 +6 v supply voltage lvdd -0.3 +4.6 v input voltage hvin lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v output voltage hvout lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage hvdd lvdd +4.75v +2.70 +3.00 +5.00v +3.00 +3.30 +5.25v +3.30 +3.60 v v v note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.3 dc characteristics (vdd=5.0v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 2 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption (dual power) dpt5v dpt3v 17 31 ma ma power consumption (single power 3.3v) spt3v 48 ma
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 28 6.4 a.c. timing characteristics 6.4.1 xtal / clock lclk/xtalin tr tf tlow clko tod symbol description min typ. max units t cyc cycle time 40* ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to clko out delay 10 * note : the tcyc can be from 16.6ns to 50ns, that is frequency from 60mhz to 20mhz. 6.4.2 reset timing lclk reset symbol description min typ. max units trst reset pulse width 100 - - lclk tcyc thigh
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 29 6.4.3 attribute memory read timing tcr ta(a) th(a) a[9:0], reg# ta(ce) tv(a) tsu(ce) ce# tsu(a) ta(oe) th(ce) oe# tv(wt-oe) tw(wt) tdis(ce) wait# ten(oe) tv(wt) tdis(oe) d[15:0] data valid symbol description min typ. max units t cr read cycle time 300 - - ns t a(a) address access time - - 120 ns t a(ce) card enable access time - - 100 ns t a(oe) output enable access time - - 100 ns t dis(oe) output disable time from oe# 0.5 - - ns t en(oe) output enable time from oe# - - 100 ns t v(a) data valid from address change 0 - - ns t su(a) address setup time 30 - - ns t h(a) address hold time 20 - - ns t su(ce) card enable setup time 0 - - ns t h(ce) card enable hold time 20 - - ns t v(wt-oe) wait# valid from oe# - - 10 ns t w(wt) wait# pulse width - - 200 ns t v(wt) data setup for wait# released 100 - - ns
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 30 6.4.4 attribute memory write timing tcw a[9:0], reg# tsu(ce-weh) ce# tsu(ce) tsu(a-weh) th(ce) oe# tsu(a) tw(we) trec(we) we# tv(wt-we) tv(wt) tw(wt) th(oe-we) wait# tsu(oe-we) tsu(d-weh) th(d) d[15:0](din) data input establish tdis(we) ten(oe) tdis(oe) ten(we) d[15:0](dout) symbol description min typ. max units t cw write cycle time 250 - - ns t w(we) write pulse width 150 - - ns t su(a) address setup time 30 - - ns t su(a-weh) address setup time for we# 180 - - ns t su(ce-weh) card enable setup time for we# 180 - - ns t su(d-weh) data setup time for we# 80 - - ns t h(d) data hold time 30 - - ns t rec(we) write recover time 30 - - ns t dis(we) output disable time from we# - - 5 ns t dis(oe) output disable time from oe# - - 5 ns t en(we) output enable time from we# 5 - - ns t en(oe) output enable time from oe# 5 - - ns t su(oe-we) output enable setup time from oe# 10 - - ns t h(oe-we) output enable hold time from oe# 10 - - ns t su(ce) card enable setup time 0 - - ns t h(ce) card enable hold time 20 - - ns t v(wt-we) wait# valid from we# - - 15 ns t w(wt) wait# pulse width - - 200 ns t v(wt) we# high from wait# released 0 - - ns
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 31 6.4.5 i/o read timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iord# tsua tdrinpack inpack# tdfinpack tdriois16 iois16# tdfiois16 td tdr(wt) wait# tdfwt tw(wt) th d[15:0] data valid symbol description min typ. max units t d data delay after iord# - - 50 ns t h data hold following iord# 0.5 - - ns t w iord# width time 165 - - ns t sua address setup before iord# 70 - - ns t ha address hold before iord# 20 - - ns t suce ce# setup before iord# 5 - - ns t hce ce# hold before iord# 20 - - ns t sureg reg# setup before iord# 5 - - ns t hreg reg# hold before iord# 0 - - ns t dfinpack inpack# delay falling from iord# 0 - 10 ns t drinpack inpack# delay rising from iord# - - 10 ns t dfiois16 iois16# delay falling from address* - - 10 ns t driois16 iois16# delay rising from address* - - 0 ns t dfwt wait# delay falling from iord# - - 5 ns t dr(wt) data delay from wait# rising - - 0 us t w(wt) wait# width time - - 100 ns * note : the address includes reg# and ce1# signal
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 32 6.4.6 i/o write timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iowr# tsua tdriois16 iois16# tdfiois16 tdriowr wait# tdfwt tw(wt) th tsu d[15:0] data symbol description min typ. max units t su data setup before iowr# 60 - - ns t h data hold following iowr# 30 - - ns t w iowr# width time 165 - - ns t sua address setup before iowr# 70 - - ns t ha address hold before iowr# 20 - - ns t suce ce# setup before iowr# 5 - - ns t hce ce# hold before iowr# 20 - - ns t sureg reg# setup before iowr# 5 - - ns t hreg reg# hold before iowr# 0 - - ns t dfiois16 iois16# delay falling from address* - - 10 ns t driois16 iois16# delay rising from address* - - 0 ns t dfwt wait# delay falling from iowr# - - ** ns t w(wt) wait# width time - - ** ns t driowr iowr# high from wait# high 0 - - us *note : the address includes reg# and ce1# signal ** note : there is no wait state while i/o write operation
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 33 6.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 34 6.4.8 sni timing ttclk ttch ttcl stxc ttv tth stxd stxe trclk trch trcl srxc trs trh srxd scrs symbol description min typ. max units ttclk cycle time(10mbps) - 100 - ns ttch high time(10mbps) 45 - 55 ns trch low time(10mbps) 45 - 55 ns ttv clock to data valid - - 26 ns tth data output hold time 5 - - ns trclk cycle time(10mbps) - 100 - ns trch high time(10mbps) 45 - 55 ns trcl low time(10mbps) 45 - 55 ns trs data setup time 10 - - ns trh data hold time 5 - - ns
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 35 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.1 a2 1.3 1.4 1.5 a 1.7 b 0.155 0.16 0.26 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.60 16.00 16.40 he 15.60 16.00 16.40 l 0.30 0.50 0.70 l1 1.00 q 0 10
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 36 appendix a: application note a.1 using crystal 25mhz or 20mhz AX88190a to phy clko 25mhz xtalin xtalout 25mhz crystal 8pf 2mohm 8pf note : the capacitors (8pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator 25mhz or 20mhz AX88190a to phy clko 20mhz xtalin xtalout nc 3.3v power osc 20mhz a.3 using 60mhz oscillator/crystal AX88190a to phy clko 60mhz clk_div3# pull low 20mhz xtalin xtalout nc 3.3v po wer osc 60mhz devided by 3
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 37 a.4 dual power (5v and 3.3v) application +5v +5v +3.3v (option for core logic) +5v hvdd +5v +3.3v lvdd a.5 single power (3.3v) application +3.3v +3.3v +3.3v hvdd +3.3v +3.3v lvdd AX88190a phy/txrx modem daa magnetic rj45 rj11 +5v pcmcia i/f eeprom AX88190a phy/txrx modem daa magnetic rj45 rj11 +3.3v pcmcia i/f eeprom
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 38 a.6 dual power (5v and 3.3v) application with 3.3v phy the 510 and 1k ohm resisters are just for voltage adjustment AX88190a phy rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio 510 ohm 1k ohm
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 39 appendix b: AX88190 design changes to AX88190a please refer to following circuit diagram that implement in AX88190 pwb and follow the following four steps. 1. remove AX88190 and replace with AX88190a 2. remove 2 pieces of buffer memory(32k*8 sram). because they are not necessary anymore. 3. remove 74f86 and 74f74 ttl ic 4. shorten the jumper shown as below circuit diagram lable ? jumper for future use ? from pcmcia connector pin 9 from AX88190 pin 101 to AX88190 pin 16 jumper for future use clk25m oe_# oe_m# u1b 74f74 d 12 clk 11 q 9 q 8 pr 10 cl 13 u1a 74f74 d 2 clk 3 q 5 q 6 pr 4 cl 1 u2a 74f86 1 2 3
AX88190a pcmcia fast ethernet mac controller asix electronics corporation 40 errata of AX88190a version ed2 1. sni (serial network interface) has bug for homepna application. solution: using mii interface for homepna solution. refer to ? demonstration circuit ? on page 39 to 44.
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 41 demonstration circuit : AX88190a + ethernet phy + homepna 1m8 phy vcc gnd spkr# sa8 sd7 AX88190al 10base-t/100base-tx & 1m homepna application with dp83846a & dp83851 phyceiver. (reference only) ce2# 3.3v sd8 oe# iowr# vcc r40 1k inpack# sa5 reset iois16# sd1 iowr# ireq# sd5 gnd sd14 iord# 3.3v ce2# gnd sa3 we# + c10 4.7uf/16v ireq# sa0 sd15 ce1# gnd gnd vcc vcc iord# inpack# we# inpack# stschg# sa1 gnd reg# oe# sa7 sd12 gnd iois16# sd2 iord# iowr# stschg# spkr# + c1 4.7uf/16v u4 pcmcia-68 icm-68fyc-om03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 gnd d3 d4 d5 d6 d7 ce1# a10 oe# a11 a9 a8 a13 a14 we# ireq# vcc vpp1 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 iois16# gnd gnd cd1# d11 d12 d13 d14 d15 ce2# vs1# iord# iowr# a17 a18 a19 a20 a21 vcc vpp2 a22 a23 a24 a25 vs2# reset wait# inpack# reg# spkr# stschg# d8 d9 d10 cd2# gnd r40 : option for 3.3v card tpye. ce2# wait# sd13 c9 0.01u ireq# we# ce1# reg# c12 0.01u wait# reset reset sa9 gnd sd9 sa6 ce1# spkr# stschg# gnd sd11 sd0 wait# vcc sa4 gnd sa2 3.3v sd[0..15] u7 ams117 1 4 2 3 adj/gnd tab/out out in sd6 sa[0..9] c32 0.01u + c8 4.7uf/16v oe# reg# sd4 sd3 sd10 iois16# vcc
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 42 rxclk r22 10k 3.3v inpack# oe# sa1 txd3 spkr# r21 10k pclk gnd r7 2m inpack# rxd1 xin ce2# ireq# col eedo txd0 rxd2 c19 0.1u rxdv r25 10k rxd1 rxer iord# iois16# rxdv gnd sd13 reset# c25 0.1u txen col pclk mdc gnd sd8 crs eedi sd10 col oe# 3.3v txclk ireq# gnd sd2 sa9 iowr# spkr# rxd0 txen (r23 : option for use 93c46) 5v gnd eedo iois16# 5v sd15 (r22 : option for test) spkr# oe# sd11 3.3v sd1 iois16# ce1# reset# sd[0..15] rxd2 iord# sd5 iowr# 5v sa8 iowr# rxd3 reset vcc stschg# sa5 rxd3 sa0 sd7 c23 0.1u 3.3v reg# we# txd1 eecs txen 3.3v r2 4.7k eesk eecs r6 10k ireq# ce1# eedi wait# rxer sa3 wait# sa[0..9] pclk sd9 rxd[0..3] 3.3v sa4 (r42 : option for reserved) sd14 c17 8p reset y1 25mhz-crystal wait# we# crs c16 0.1u xout sa2 mdc mdio u1 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc rxclk iord# c18 8p reset crs xin mdio rxdv sd0 r41 10k inpack# mdio reg# reset# mdc we# txclk ce2# 5v sd3 rxd0 u5 AX88190al 1 2 3 4 5 6 7 8 9 10 38 37 36 35 33 32 31 30 28 27 26 25 23 22 21 20 18 16 13 12 120 17 15 14 127 125 124 123 122 121 19 29 64 75 44 54 100 110 126 128 11 24 34 39 40 49 59 69 81 93 102 105 119 111 112 113 115 116 117 118 68 70 74 82 83 84 85 86 87 88 89 90 94 95 96 97 98 99 91 92 106 107 108 109 114 104 103 101 77 73 61 60 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 ce1# oe# we# ireq# iois16# ce2# iord# iowr# reset wait# inpack# reg# spkr# stschg# hvdd hvdd hvdd hvdd lvdd lvdd lvdd lvdd lvdd lvdd vss vss vss vss vss vss vss vss vss vss vss vss vss mdcs# mmint maudio mrin# mpwdn mreset# mrdy mpd_set ppd_set slink# rx_er rx_dv col crs rx_clk rxd0 rxd1 rxd2 rxd3 tx_clk tx_en txd0 txd1 txd2 txd3 mdio mdc eecs eeck eedi eedo ppwdn xtalout lclk/xtalin clko25m test# eeprom size gpi0 gpi1 sa7 r23 10k stschg# sa6 ce1# rxclk rxd[0..3] txd2 rxer sd6 sd4 sd12 xout r42 10k c20 0.1u stschg# 3.3v r8 20 ce2# eesk reg# txclk c24 0.1u txd[0..3]
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 43 reset# r1 4.7k hspdled txd1 actled set phy address to 00000. 3.3v gnd c13 0.1u r17 510 tip 3.3va1 txclk pwrled hcolled actled 3.3v spdled rxclk 3.3v rxd2 pwrled rxd3 rxd3 colled crs hactled txen txen pclk hactled crs r14 510 c14 0.1u 3.3v hcolled r20 9.31k 1% l1 f.b. gnd txclk rxd1 hspdled txclk txd0 + c7 4.7uf/16v hspdled 3.3va1 u3 dp83851 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 19 29 39 5 11 20 7 8 4 17 18 16 15 44 14 42 43 48 30 40 41 47 3 6 10 1 2 9 12 13 txd3 txd2 txd1 txd0/txd tx_en tx_clk rxd3/phyad0 rxd2/cmddis# rxd1/hi_power_en# rxd0/rxd/low_speed_en# rx_dv/gpsi_sel# rx_clk col/mdio_int_en# crs/pin_intrp_en# mdio mdc x1 x2 io_vdd1 io_vdd2 core_vdd ana_vdd2 ana_vdd3 io_gnd1 tip ring rbias led_col/phyad2 led_act/phyad1 led_speed/phyad3 led_power/phyad4 reset# reserved reserved reserved ana_vdd1 io_gnd2 core_gnd core_sub(0v) ana_gnd1 ana_gnd2 ana_gnd3 ana_gnd4 sub_gnd1 sub_gnd2 sub_gnd3 reserved reserved mdc mdio col 3.3v r16 510 tip 3.3v c15 0.1u txd3 ring colled 3.3va2 3.3va2 hcolled txd[0..3] pclk txd[0..3] rxclk spdled c26 0.1u c4 0.1u pclk rxdv ring gnd r13 4.7k rxd[0..3] c21 0.1u mdc mdio rxd3 r18 20 r4 4.7k reset# 3.3v txd2 gnd spdled txen col tip rxdv r3 4.7k rxd0 rxd2 hactled gnd rxdv l2 f.b. col crs mdc gnd rxd1 mdio r5 4.7k c5 0.1u r19 20 rxd0 actled ring reset# rxd[0..3] rxclk colled r15 4.7k
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 44 txd1 tdp r30 510 r12 4.7k rdn c31 0.1u l4 f.b. txclk fled gnd phyad1 pclk 3.3v rxdv txen l3 f.b. reset# txd3 lnkled rxd1 c41 0.01u rled tled r47 9.31k mdio gnd c22 0.01u mdio tdn pclk lnkled rxdv txclk rxer rxd1 c35 0.1u reset# c27 0.1u r43 4.7k rled col r32 510 3.3va1 spdled txd[0..3] sled c34 0.1u gnd 3.3v actled r24 4.7k rdp 3.3v tled spdled tdp 3.3v rdn tled 3.3v rdp lled cled crs actled phyad2 rxer pclk 3.3va2 tdn txd2 crs rxd[0..3] r11 4.7k u8 dp83846a 59 58 55 54 52 51 38 39 40 41 44 45 60 61 36 37 67 66 57 65 12 14 64 3 7 23 73 2 9 13 15 18 19 76 79 50 46 16 17 11 10 1 5 8 20 21 22 47 63 68 69 70 71 74 75 77 78 80 6 48 34 42 53 56 4 24 49 72 43 35 62 33 32 31 30 29 28 27 26 25 txd3 txd2 txd1 txd0 tx_en tx_clk rxd3 rxd2 rxd1 rxd0 rx_dv rx_clk col crs/led_cfg# mdio mdc x1 x2 io_vdd io_vdd ana_vdd2 ana_vdd3 io_gnd rbias ana_vdd1 core_gnd core_gnd ana_gnd ana_gnd ana_gnd ana_gnd ana_gnd sub_gnd sub_gnd sub_gnd tx_er rx_er/pause_en# td+ td- rd+ rd- reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved ana_gnd core_gnd io_gnd io_gnd io_gnd io_gnd ana_vdd core_vdd core_vdd core_vdd io_vdd io_vdd reset# led_dplx/phy0 led_col/phy1 led_gdlnk/phy2 led_tx/phy3 led_rx/phy4 led_speed an_en an_1 an_0 r44 20 reset# lled phyad3 phyad4 txd0 rxclk r27 20 rxd2 mdc c39 0.1u crs cled tdn rxd2 r28 4.7k phyad0 rdp txd[0..3] rxd0 rled to pcmj15 connect rxd3 r45 4.7k tdp 3.3va2 r29 510 r26 4.7k transmit activity : used r29. receive activity : used r30. transmit/receive activity : d1 & d2 & r31. rxclk gnd mdio actled rxd[0..3] mdc lled 3.3v lnkled c33 0.1u txen rxclk txclk txen 3.3v 3.3v rxd0 r31 510 gnd by pass cap with digital power supply fled rxdv r33 510 rxer by pass cap with analog power supply sled spdled gnd set phy address to 00011 rdn r45 : setting fdpx led (option) 3.3va1 d2 1n4148 gnd col c29 0.1u rxd3 d1 1n4148 mdc col
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 45 tdp c38 10p rdn spdled c43 0.01u tip r38 75 rdp ring j1 pcmcia-15 rmc-e15my-om-ma2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3.3v c28 0.01u gnd rdp r34 49.9 1% c11 0.01u/2kv lnkled r35 49.9 1% ring c36 10p hspdled c3 0.01u/2kv hactled r48 75 c42 10p tdn u6 16st0009p 6 7 8 1 2 3 11 10 9 16 15 14 ct td+ td- rd+ rd- ct ct tx+ tx- rx+ rx- ct tip actled hactled hcolled spdled rx+ rx+ c37 0.01u gnd r39 75 actled tdn lring tx+ rdn r10 49.9 1% r37 75 c6 0.1u tx- tip tdn lnkled r46 49.9 1% chassis hactled tdp actled 3.3v ring r9 49.9 1% rdp c40 0.1u rdn ltip lnkled rx- 3.3v 3.3v tx- r49 1m rx- lring u2 lhr002 4 6 1 2 11 9 14 13 tut+ tut- z+ z- tip+ ring- c+ c- c2 p0800sa ltip spdled r36 49.9 1% hspdled hcolled hspdled hcolled gnd tdp c30 10p tx+
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 46 d5 led hactled spdled d8 led d4 led j3 con8 1 2 3 4 5 6 7 8 d6 led tx+ homepna collision led tx+ hactled rx- 10/100m collision led r45 lnkled hcolled rx+ d3 led homepna speed led rx+ tx- ltip hcolled 10/100mspeed led actled gnd tx- j4 rj45n 1 2 3 6 4 5 7 8 lnkled j5 con8 1 2 3 4 5 6 7 8 actled lring gnd r78 hspdled r45 homepna activity led hspdled r78 d7 led ltip spdled rx- j2 rj11-s 1 2 3 4 5 6 nc a1 tip ring a2 nc 10/100m link led lring
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 47 reference bill of materials item quantity reference part reamrk 1 2 c18,c17 8p 0603 2 4 c30,c36,c38,c42 10p 0603 3 8 c9,c12,c22,c28,c32,c37,c41,c43 0.01u f 0603 4 22 c4,c5,c6,c13,c14,c15,c16,c19,c20,c21,c23,c24,c25,c26,c27,c29,c31,c33,c34,c35,c39,c40 0.1u f 0603 5 4 c1,c7,c8,c10 4.7uf/16v 1206 6 2 c11,c3 0.01u/2kv 1206 7 1 c2 p0800sa *1 8 2 d2,d1 1n4148 smd 9 6 d3,d4,d5,d6,d7,d8 led dip 10 4 l1,l2,l3,l4 f.b 1206 11 5 r8,r18,r19,r27,r44 20 0603 12 4 r37,r38,r39,r48 75 0603 13 5 r9,r10,r35,r46 ,r34,r36 49.9 1% 0603 14 5 r14,r16,r17,r32,r33 510 0603 14-1 1 r31 330 0603 15 13 r1,r2,r3,r4,r5,r11,r12,r13,r15,r24,r26,r28,r43 4.7k 0603 16 2 r47,r20 9.31k 1% 0603 17 4 r6,r21 ,r25 ,r4 2 10k 0603 18 1 r49 1m 0603 19 1 r7 2m 0603 20 1 u5 AX88190al tqfp 21 1 u1 93c56 smd 22 1 u2 lhr002 *2 23 1 u6 16st0009p *2 24 1 u3 dp83851 *3 25 1 u8 dp83846a *3 26 1 u7 ams117 smd 27 1 y1 25mhz crystal dip 28 1 j2 rj11 dip 39 2 j3,j5 con8 dip 30 1 j4 rj45 dip 31 1 j1 pcm cia-15 *4 32 1 u4 pcmcia -68 *4
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 48 sponsors of components components company contect person telephone sidactor ( p0800sa ) gid gloria international jason hsu 02-2506 8371 transformers bothhand enterprise inc. dennis fan 03-3698237 phyceiver national semiconductor henry chou 02-25370217 honda pcmcia connectors & frames yun hui ltd. zong-ming chen 02-27669242
AX88190a 10/100mbps pcmcia fast ethernet mac controller asix electronics corporation 49 sponsors of components (chinese) components company contect person telephone sidactor ( p0800sa ) gid gloria international oa_??|3--?q jason hsu ?}a?? 02-2506 8371 transformers bothhand enterprise inc. ?-o~a?|3--?q dennis fan -s| 03-3698237 phyceiver national semiconductor henry chou ?p??? 02-25370217 honda pcmcia connectors & frames 1?|3--?q 3`? 02-27669242

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